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<div class="header">
  <div class="headertitle"><div class="title">ADC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
</div><!--header-->
<div class="contents">

<p>Analog to Digital Converter.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
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<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Analog to Digital Converter. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a02a34c693903ef6ac7326ed02582fdcf" name="a02a34c693903ef6ac7326ed02582fdcf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a02a34c693903ef6ac7326ed02582fdcf">&#9670;&#160;</a></span>AWD2CR</h2>

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<p>ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a3be9b42a9cf52d1b6776c2cfa439592f">&#9670;&#160;</a></span>AWD3CR</h2>

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<p>ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae2a9ddff6ae4c52a011f8f5fa15d8b57">&#9670;&#160;</a></span>CALFACT2_RES14</h2>

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<p>ADC Linearity Calibration Factors specific ADC1/2, Address offset: 0xC8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#acb8f02ad1b8f9e65955fc11f47ef2e4b">&#9670;&#160;</a></span>CALFACT_RES13</h2>

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<p>ADC Calibration Factors specific ADC1/2, Address offset: 0xC4 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a40a83116e2176d7197fc4b7d0eb08609">&#9670;&#160;</a></span>CFGR</h2>

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<p>ADC Configuration register, Address offset: 0x0C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a0a4c0d337b0e546e549678b77ea63246">&#9670;&#160;</a></span>CFGR2</h2>

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<p>ADC Configuration register 2, Address offset: 0x10 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6126350919b341bfb13c0b24b30dc22a">&#9670;&#160;</a></span>CR</h2>

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<p>ADC control register, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a91cccc0d0a05c3c9e0a76efffa423793">&#9670;&#160;</a></span>DIFSEL_RES12</h2>

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<p>ADC Differential Mode Selection Register specific ADC1/2, Address offset: 0xC0 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a84114accead82bd11a0e12a429cdfed9">&#9670;&#160;</a></span>DR</h2>

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<p>ADC regular data register, Address offset: 0x40 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a012000126b1fd446887857938a6c4614">&#9670;&#160;</a></span>HTR1_TR2</h2>

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<p>ADC watchdog higher threshold register 1, Address offset: 0x24 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a7de1ecd49b58ac466fda27aef6e63e52">&#9670;&#160;</a></span>HTR2_CALFACT</h2>

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<p>ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset: 0xB4 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aeffc64da996c494b9eaf92fb31e66a61">&#9670;&#160;</a></span>HTR3_RES11</h2>

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<p>ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset: 0xBC </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a78d24b9deed83e90a2ff96c95ba94934">&#9670;&#160;</a></span>IER</h2>

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<p>ADC Interrupt Enable Register, Address offset: 0x04 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#add06351bbb4cf771125247d62b145d75">&#9670;&#160;</a></span>ISR</h2>

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<p>ADC Interrupt and Status Register, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab4b0a79a9e4a9d5b0a24d7285cf55bdc">&#9670;&#160;</a></span>JDR1</h2>

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<p>ADC injected data register 1, Address offset: 0x80 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a898b87cab4f099bcca981cc4c9318b51">&#9670;&#160;</a></span>JDR2</h2>

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<p>ADC injected data register 2, Address offset: 0x84 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a40999cd0a255ef62b2340e2726695063">&#9670;&#160;</a></span>JDR3</h2>

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<p>ADC injected data register 3, Address offset: 0x88 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#abae6e9d688b16ef350878998f5e21c0b">&#9670;&#160;</a></span>JDR4</h2>

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<p>ADC injected data register 4, Address offset: 0x8C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a5438a76a93ac1bd2526e92ef298dc193">&#9670;&#160;</a></span>JSQR</h2>

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<p>ADC injected sequence register, Address offset: 0x4C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af1d4e31442e2cdebc1f76b78b095a8ae">&#9670;&#160;</a></span>LTR1_TR1</h2>

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<p>ADC watchdog Lower threshold register 1, Address offset: 0x20 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac330f007ceb75f385a62443e8ddd9c0d">&#9670;&#160;</a></span>LTR2_DIFSEL</h2>

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<p>ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset: 0xB0 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8efc5085ede3544de60dce2979fff160">&#9670;&#160;</a></span>LTR3_RES10</h2>

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<p>ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset: 0xB8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a97988c41c381690e8a38fec8d2d24ca5">&#9670;&#160;</a></span>OFR1</h2>

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<p>ADC offset register 1, Address offset: 0x60 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae446fdae782b6dd059e348fc877681a6">&#9670;&#160;</a></span>OFR2</h2>

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<p>ADC offset register 2, Address offset: 0x64 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a23083f97baee16e0002366547c8cb5ea">&#9670;&#160;</a></span>OFR3</h2>

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<p>ADC offset register 3, Address offset: 0x68 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a232fcdf46374a9c267c2a6533a777fac">&#9670;&#160;</a></span>OFR4</h2>

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<p>ADC offset register 4, Address offset: 0x6C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac73ab76ad0855b2f4b49df96ab954516">&#9670;&#160;</a></span>PCSEL_RES0</h2>

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<p>Reserved for ADC3, ADC1/2 pre-channel selection, Address offset: 0x1C </p>

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<p>Reserved for ADC1/2, ADC3 threshold register, Address offset: 0x28 </p>

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<p>Reserved, 0x02C </p>

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<p>Reserved, 0x044 </p>

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<p>Reserved, 0x048 </p>

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<p>Reserved, 0x050 - 0x05C </p>

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<p>Reserved, 0x070 - 0x07C </p>

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<p>Reserved, 0x090 - 0x09C </p>

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<p>Reserved, 0x0A8 </p>

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<p>Reserved, 0x0AC </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a73009a8122fcc628f467a4e997109347">&#9670;&#160;</a></span>SMPR1</h2>

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<p>ADC sample time register 1, Address offset: 0x14 </p>

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<p>ADC sample time register 2, Address offset: 0x18 </p>

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<p>ADC regular sequence register 1, Address offset: 0x30 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6b6e55e6c667042e5a46a76518b73d5a">&#9670;&#160;</a></span>SQR2</h2>

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<p>ADC regular sequence register 2, Address offset: 0x34 </p>

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<p>ADC regular sequence register 3, Address offset: 0x38 </p>

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<p>ADC regular sequence register 4, Address offset: 0x3C </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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